High mobility strained channels for fin-based transistors

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United States of America Patent

PATENT NO 9184294
SERIAL NO

14494968

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Abstract

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Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aubertine, Daniel B North Plains, US 25 645
Cea, Stephen M Hillsboro, US 123 2785
Ghani, Tahir Portland, US 701 6999
Glass, Glenn A Beaverton, US 178 4433
Kavalieros, Jack T Portland, US 512 7917
Kotlyar, Roza Portland, US 54 783
Murthy, Anand S Portland, US 310 5611

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