Speculative non-faulting loads and gathers
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Nov 17, 2015
Grant Date -
Jun 26, 2014
app pub date -
Dec 21, 2012
filing date -
Dec 21, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand.
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