Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
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United States of America Patent
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Nov 17, 2015
Grant Date -
Jul 10, 2014
app pub date -
Jan 13, 2014
filing date -
Apr 8, 2009
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Abstract
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
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Patent Owner(s)
Patent Owner | Address | |
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SANDISK TECHNOLOGIES LLC | 6900 DALLAS PARKWAY SUITE 325 PLANO TX 75024 |
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Inventor Name | Address | # of filed Patents | Total Citations |
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Samachisa, George | Milpitas, US | 88 | 5696 |
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