Nonvolatile semiconductor memory device
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United States of America Patent
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Nov 17, 2015
Grant Date -
Sep 17, 2015
app pub date -
Aug 19, 2014
filing date -
Mar 11, 2014
priority date (Note) -
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Abstract
The voltage switching circuit comprises: an nMOS transistor having a gate connected to a first terminal that outputs an output voltage, a drain connected to a power-supply terminal, and a source connected to a second terminal; a first pMOS transistor having a source connected to the second terminal, a drain connected to the first terminal, and a gate provided with a first or second voltage, a source and a well thereof being short-circuited; and a switching circuit connected between a third terminal that supplies the input voltage and the first terminal and configured to turn on when the output voltage is supplied to the first terminal. A gate electrode of the first pMOS transistor is configured by semiconductor including p-type impurity. A concentration of p-type impurity in the gate electrode of the memory cell is different from that of the first pMOS transistor.
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