Bump structure with underbump metallization structure and integrated redistribution layer

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United States of America Patent

PATENT NO 9190373
APP PUB NO 20120049356A1
SERIAL NO

13222332

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Abstract

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According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ezawa, Hirokazu Tokyo, JP 47 915
Migita, Tatsuo Oita, JP 24 107
Shima, Masaya Kanagawa, JP 13 33
Yamashita, Soichi Kanagawa, JP 19 162

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