Semiconductor memory device and production method thereof
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United States of America Patent
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Nov 17, 2015
Grant Date -
Nov 6, 2014
app pub date -
Sep 9, 2013
filing date -
May 3, 2013
priority date (Note) -
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Abstract
A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.
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