HIGH-VOLTAGE LEVEL CONVERSION CIRCUIT
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United States of America Patent
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Nov 17, 2015
Grant Date -
Nov 26, 2015
app pub date -
Aug 21, 2014
filing date -
May 21, 2014
priority date (Note) -
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Abstract
The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.
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