AES encryption/decryption circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9191197
APP PUB NO 20090097639A1
SERIAL NO

12236905

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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This invention makes the number of cycles required for AES encryption or decryption by hardware smaller than before by reducing the difference among the summation of the signal processing time for each sub-block transformations in each clock cycle period. To do this, an encryption/decryption circuit includes a first AddRoundKey Transformation module, a second AddRoundKey Transformation module, a ShiftRows Transformation module, a SubBytes Transformation module, a MixColumns Transformation module, and a data holding unit, wherein in a cycle of encryption, the first AddRoundKey Transformation module and the second AddRoundKey Transformation module are executed using different Round Keys.

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First Claim

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Patent Owner(s)

  • CANON KABUSHIKI KAISHA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hotta, Hirohisa Kawasaki, JP 3 32
Yushiya, Akihiko Tokyo, JP 22 200

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