Dead block predictors for cooperative execution in the last level cache

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United States of America Patent

PATENT NO 9195606
APP PUB NO 20140351524A1
SERIAL NO

13976248

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A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bashyam, Nithiyanandan Bangalore, IN 4 49
Chaudhuri, Mainak Bangalore, IN 5 44
Guar, Jayesh Bangalore, IN 1 19
Natarajan, Ragavendra Mysore, IN 11 42
Subramoney, Sreenivas Bangalore, IN 98 403

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