Common shared memory in a verification system

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United States of America Patent

PATENT NO 9195784
APP PUB NO 20110307233A1
SERIAL NO

13078786

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Abstract

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The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

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Patent Owner(s)

  • CADENCE DESIGN SYSTEMS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Sharon Sheau-Pyng Cupertino, US 11 1199
Shen, Quincy Kun-Hsu Saratoga, US 5 604
Tsai, Mike Mon Yen Los Altos Hills, US 4 451
Tseng, Ping-Sheng Sunnyvale, US 21 1798
Wang, Steven Cupertino, US 69 1053

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