Method and apparatus for a zero voltage processor

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United States of America Patent

PATENT NO 9235258
SERIAL NO

14254413

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Abstract

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Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Conrad, John B Folsom, US 10 149
Fischer, Stephen A Gold River, US 97 1630
George, Varghese Folsom, US 164 1311
Jahagirdar, Sanjeev Folsom, US 99 1235
Milstrey, Robert Citrus Heights, US 18 152
Naveh, Alon Ramat Hasharon, IL 105 2716
Rotem, Shai Haifa, IL 28 380

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