Methodology for preventing functional failure caused by CDM ESD
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United States of America Patent
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Jan 19, 2016
Grant Date -
Apr 22, 2010
app pub date -
Oct 21, 2008
filing date -
Oct 21, 2008
priority date (Note) -
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Abstract
A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.
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