Wordline resistance reduction method and structure in an integrated circuit memory device
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United States of America Patent
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Jan 19, 2016
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app pub date -
Dec 6, 2010
filing date -
Apr 29, 2008
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Abstract
Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
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