Methods of forming nanoscale floating gate

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United States of America Patent

PATENT NO 9240495
APP PUB NO 20130187215A1
SERIAL NO

13795927

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Abstract

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A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ramaswamy, D V Nirmal Boise, US 91 654
Sandhu, Gurtej S Boise, US 1216 32355

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