Programmable micro-core processors for packet parsing with packet ordering

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United States of America Patent

PATENT NO 9244798
SERIAL NO

13164533

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Abstract

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Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hass, David T Santa Clara, US 54 1225
Kuila, Kaushik San Jose, US 10 128

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