Reduced wake up delay for on-die routers

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9250679
SERIAL NO

13791574

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dai, Donglai Pleasanton, US 13 200
Kumar, Akhilesh Sunnyvale, US 70 975
Park, Dongkook Santa Clara, US 6 14

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