Power isolation for memory backup

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9251005
APP PUB NO 20120159060A1
SERIAL NO

13081095

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Abstract

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Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chon, Peter B Cypress, US 5 113
Piccirillo, Gary J Cypress, US 39 2281
Yu, James Houston, US 40 479

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