Implementing enhanced reliability of systems utilizing dual port DRAM
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United States of America Patent
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Feb 2, 2016
Grant Date -
Oct 1, 2015
app pub date -
Mar 27, 2014
filing date -
Mar 27, 2014
priority date (Note) -
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Abstract
A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.
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