Infrastructure for performance based chip-to-chip stacking
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United States of America Patent
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Feb 2, 2016
Grant Date -
Dec 13, 2012
app pub date -
Jun 9, 2011
filing date -
Jun 9, 2011
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Abstract
A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
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