Test control circuit, semiconductor memory device and method for testing the same
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United States of America Patent
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Feb 2, 2016
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N/A
app pub date -
Aug 28, 2014
filing date -
Aug 28, 2014
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Abstract
Disclosed herein are test control circuit, semiconductor memory device, and testing method embodiments for suppressing variations in test time while reducing the influence of a failed cell. An embodiment operates by performing a first verify of a cell selected in a predetermined order; storing an address of the cell when the first verify is a fail until the number of addresses is a predetermined number; applying a predetermined voltage to a plurality of cells of an erase unit when a next fail is determined in the first verify after the predetermined number of addresses have been stored; and performing a second verify to one or more cells indicated by the predetermined number of addresses, wherein the first verify is performed from a cell at the next fail according to the predetermined order after the second verify has finished.
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