Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
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United States of America Patent
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Feb 2, 2016
Grant Date -
Dec 27, 2012
app pub date -
Sep 6, 2012
filing date -
May 4, 2011
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Abstract
A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.
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