Shielded gate trench MOS with improved source pickup layout
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United States of America Patent
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Feb 2, 2016
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N/A
app pub date -
Mar 17, 2015
filing date -
Mar 11, 2010
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Abstract
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
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