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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
LATTICE SEMICONDUCTOR CORPORATION	5555 NE MOORE CT HILLSBORO OR 97124

International Classification(s)

• H03K:PULSE TECHNIQUE

• [Classification Symbol]

• [Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Gunaratna, Senani	Los Gatos, US	13	51
Sharpe-Geisler, Brad	San Jose, US	30	172
Yew, Ting	San Jose, US	13	41

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date
11.5 Year Payment	$7400.00	$3700.00	$1850.00	Aug 2, 2027

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge - 11.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
February 02, 2016	US,9252755,B1   US9252755B1	GRANTED PATENT AS FIRST PUBLICATION
January 28, 2016	US,20160028383,A1   US20160028383A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 9252755

Shared logic for multiple registers with asynchronous initialization

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