Return-to-zero digital-to-analog converter with overlapping time delayed pulse generation
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United States of America Patent
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Feb 2, 2016
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app pub date -
Oct 31, 2014
filing date -
Oct 31, 2014
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Abstract
The embodiments described herein provide a digital-to-analog converter (DAC). The DAC implements a stepped return-to-zero (RZ) pulse scheme, where the DAC output includes the superposition of multiple time-offset RZ pulses. In one embodiment, the DAC includes a first switching element, a second switching element, a current source, and a current sink. The first switching element generates first RZ pulses, and the second switching element generates second RZ pulses, where the second RZ pulses are time-offset from the first RZ pulses. The first RZ pulses and second RZ pulses are combined to provide stepped RZ pulse output signal.
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