ENHANCED RESOLUTION SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD
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United States of America Patent
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Feb 2, 2016
Grant Date -
Feb 25, 2016
app pub date -
Aug 19, 2014
filing date -
Aug 19, 2014
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Abstract
An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
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