Memory banks with shared input/output circuitry
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United States of America Patent
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Mar 1, 2016
Grant Date -
Dec 3, 2015
app pub date -
May 28, 2014
filing date -
May 28, 2014
priority date (Note) -
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Abstract
A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.
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