Single event upset protection circuit and method
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United States of America Patent
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Mar 22, 2016
Grant Date -
Dec 3, 2015
app pub date -
May 29, 2014
filing date -
May 29, 2014
priority date (Note) -
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Abstract
An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates ‘odd’ parity, and to pass the redundant data value to the output when the parity engine output indicates ‘even’ parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.
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