Hierarchical pushdown of cells and nets to any logical depth
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United States of America Patent
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Mar 29, 2016
Grant Date -
Dec 25, 2014
app pub date -
Jun 19, 2013
filing date -
Jun 19, 2013
priority date (Note) -
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Abstract
A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
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