Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling

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United States of America Patent

PATENT NO 9300443
APP PUB NO 20140281666A1
SERIAL NO

14273416

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Abstract

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A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

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Patent Owner(s)

Patent OwnerAddress
UNIQUIFY INC2030 FORTUNE DRIVE SUITE 200 SAN JOSE CA 95131

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gopalan, Mahesh Milpitas, US 25 139

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