System and method for providing cache-aware lightweight producer consumer queues

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United States of America Patent

PATENT NO 9304920
APP PUB NO 20140351519A1
SERIAL NO

13908072

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Abstract

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A multiprocessor system or a system of hardware accelerators is provided to reduce cache ping-ponging and to provide improved single producer single consumer (SPSC) queues and methods. The systems are configured for specifying separate cache attributes for inner (e.g., local) cache and outer (e.g., shared) cache for promoting lower system overhead. Separate cache attributes are specified such that shared variables are cacheable only in a cache level shared by multiple processors.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Munoz, Robert J Round Rock, US 22 398

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