Power efficient level one data cache access with pre-validated tags
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United States of America Patent
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Apr 12, 2016
Grant Date -
Aug 6, 2015
app pub date -
Mar 14, 2013
filing date -
Mar 14, 2013
priority date (Note) -
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Abstract
A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.
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