Emulated message signaled interrupts in multiprocessor systems
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United States of America Patent
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Apr 12, 2016
Grant Date -
Jun 5, 2014
app pub date -
Nov 30, 2012
filing date -
Nov 30, 2012
priority date (Note) -
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Abstract
A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address.
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