Methods of forming parallel wires of different metal materials through double patterning and fill techniques
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United States of America Patent
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Apr 12, 2016
Grant Date -
Apr 2, 2015
app pub date -
Sep 27, 2013
filing date -
Sep 27, 2013
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Abstract
An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.
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