Processing of integrated circuit for metal gate replacement
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United States of America Patent
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Apr 12, 2016
Grant Date -
N/A
app pub date -
Mar 23, 2015
filing date -
Mar 23, 2015
priority date (Note) -
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Abstract
Embodiments of the present disclosure provide a method of processing an integrated circuit (IC) structure for metal gate replacement, the method comprising: providing a structure including a first semiconductor fin and a second semiconductor fin positioned over a buried insulator layer of a silicon-on-insulator (SOI) substrate, and a gate structure positioned over the first and second semiconductor fins, wherein the gate structure includes a gate dielectric layer and a metal layer positioned over the gate dielectric layer; forming a planarizing resist over the first and second semiconductor fins, wherein the planarizing resist includes: a first organic planarizing layer (OPL), and a second OPL over the first OPL; removing a portion of the second OPL; removing an exposed portion of the first OPL and a portion of the metal layer positioned over the second semiconductor fin; and forming a replacement metal gate (RMG) over the gate dielectric layer.
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