Method, apparatus and system for performing voltage margining

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United States of America Patent

PATENT NO 9317353
APP PUB NO 20150186197A1
SERIAL NO

14140834

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ravi, Sanjay R Hillsboro, US 2 7

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