Nonvolatile semiconductor memory device with a three-dimensional structure in which sub-blocks are independently erasable

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United States of America Patent

PATENT NO 9318214
APP PUB NO 20140247664A1
SERIAL NO

14015987

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Abstract

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A memory cell array includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells which are connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks. During writing, a control unit changes a verification level to be applied to a selected word line included in a selected sub-block depending on whether or not data has been written in a non-selected sub-block.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hosono, Koji Kanagawa, JP 160 3276
Tokiwa, Naoya Kanagawa, JP 80 1106

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