Semiconductor package with package-on-package stacking capability and method of manufacturing the same
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United States of America Patent
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Apr 19, 2016
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app pub date -
Oct 14, 2014
filing date -
Nov 13, 2013
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Abstract
The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.
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