Method and system for power management for a frequency synthesizer in a GNSS receiver chip
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United States of America Patent
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Apr 26, 2016
Grant Date -
Jun 17, 2010
app pub date -
Jan 12, 2009
filing date -
Dec 12, 2008
priority date (Note) -
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Abstract
A frequency synthesizer in a GNSS receiver chip enables duty cycling operation of the frequency synthesizer. The frequency synthesizer is cycled on to generate required clock signals for the GNSS receiver chip, and cycled off during a measurement duty cycle comprising measurement available intervals and measurement unavailable intervals. A reference clock inputted to the frequency synthesizer is on during the measurement duty-cycle. During the measurement available intervals, the frequency synthesizer is cycled on to generate the required clock based on the reference clock. During the measurement unavailable intervals, the frequency synthesizer is cycled off and clock timing is maintained based on the reference clock. A number of elapsed clock cycles of the reference clock is captured for a measurement unavailable interval and transferred to a clock offset. The GNSS receiver chip processes signals received using the required clock and the clock offset in a following measurement available interval.
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