Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values

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United States of America Patent

PATENT NO 9323500
APP PUB NO 20140122555A1
SERIAL NO

13785528

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Abstract

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In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bradford, Dennis Portland, US 8 164
Fletcher, Thomas Sherwood, US 25 333
Hickmann, Brian Sherwood, US 4 67

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