Caching optimized internal instructions in loop buffer
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United States of America Patent
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Apr 26, 2016
Grant Date -
Oct 3, 2013
app pub date -
Mar 28, 2012
filing date -
Mar 28, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.
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