Semiconductor memory device having an output buffer controller
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United States of America Patent
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Apr 26, 2016
Grant Date -
Mar 5, 2015
app pub date -
Sep 3, 2014
filing date -
Sep 3, 2013
priority date (Note) -
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Abstract
A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the data output terminal, and a calibration circuit to output an n-bit first code signal for controlling each of the n first transistors. In some embodiments, the calibration circuit includes a first counter circuit to output a k-bit second code signal (k is a natural number less than n), and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal. Additional apparatus, systems, and methods are disclosed.
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