Nonvolatile memory and method for improved programming with reduced verify
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United States of America Patent
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Apr 26, 2016
Grant Date -
Oct 24, 2013
app pub date -
Jun 24, 2013
filing date -
Mar 24, 2011
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Abstract
A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
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- 15 United States
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Patent Owner(s)
- SANDISK TECHNOLOGIES LLC
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Dong, Yingda | San Jose, US | 252 | 4794 |
Hsu, Cynthia | Milpitas, US | 28 | 379 |
Oowada, Ken | Fujisawa, JP | 69 | 799 |
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