Memory device and operation method thereof
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United States of America Patent
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Apr 26, 2016
Grant Date -
N/A
app pub date -
Jun 2, 2015
filing date -
Jan 25, 2015
priority date (Note) -
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Abstract
An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.
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