Video decoding system supporting multiple standards

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United States of America Patent

PATENT NO 9329871
APP PUB NO 20120328000A1
SERIAL NO

13608192

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Abstract

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System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

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Patent Owner(s)

Patent OwnerAddress
BROADCOM CORPORATION5300 CALIFORNIA AVENUE IRVINE CA 92617

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alvarez, Jose′ R Sunnyvale, US 3 13
Hsiun, Vivian Yorba Linda, US 32 818
MacInnis, Alexander G Los Altos, US 198 3503
Xie, Xiaodong Fremont, US 139 1792
Zhong, Sheng Fremont, US 96 892

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