Power logic for memory address conversion
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United States of America Patent
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May 3, 2016
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N/A
app pub date -
Jun 25, 2013
filing date -
Jun 25, 2013
priority date (Note) -
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Abstract
In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.
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