Chip package incorporating interfacial adhesion through conductor sputtering
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United States of America Patent
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May 3, 2016
Issued Date -
N/A
app pub date -
Oct 3, 2014
filing date -
Aug 30, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.
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