Hybrid linear validation algorithm for software transactional memory (STM) systems

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United States of America Patent

PATENT NO 9336066
APP PUB NO 20090319753A1
SERIAL NO

12142097

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A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.

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  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adl-Tabatabai, Ali-Reza Santa Clara, US 134 4425
Saha, Bratin San Jose, US 90 3754
Welc, Adam Mountain View, US 8 340

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