Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
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United States of America Patent
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May 10, 2016
Grant Date -
Jan 14, 2016
app pub date -
Jul 14, 2014
filing date -
Jul 14, 2014
priority date (Note) -
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Abstract
Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.
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