Error checking using serial collection of error data
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United States of America Patent
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May 17, 2016
Grant Date -
Sep 17, 2015
app pub date -
Sep 30, 2014
filing date -
Mar 14, 2014
priority date (Note) -
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Abstract
Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.
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