Bus circuits for memory devices
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United States of America Patent
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May 17, 2016
Grant Date -
Mar 10, 2016
app pub date -
Sep 5, 2014
filing date -
Sep 5, 2014
priority date (Note) -
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Abstract
Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.
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